1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to an internal voltage generation circuit of a semiconductor device and a method for operating the same.
2. Description of the Related Art
Most semiconductor devices including DRAM use plural internal voltages having a different level, which are generated from external voltages VDD and VSS, in addition to the external voltages. Typically, the semiconductor devices generate the internal voltages through a charge pumping method or voltage down converting method, using a reference voltage corresponding to a target level, an external power supply voltage VDD, and an external ground voltage VSS.
In the case of DRAM, the internal voltages generated by the charge pumping method may include a boost voltage VPP, a back bias voltage VBB, and the like. Furthermore, the internal voltages generated by the voltage down converting method may include a core voltage VCORE, a bit line precharge voltage VBLP, and the like.
The boost voltage VPP has a voltage level greater than the external power supply voltage VDD, and is mainly used for activating word lines.
FIG. 1 is a block diagram illustrating an internal voltage generation circuit of a conventional semiconductor device.
Referring to FIG. 1, the internal voltage generation circuit includes a pumping voltage detection unit 10, an oscillation signal generation unit 20, and a pumping unit 30. The pumping voltage detection unit 10 detects a level of a pumping voltage VPUMP based on a reference pumping level PUMP_VREF to output a pumping detection signal PUMP_DET. The oscillation signal generation unit 20 generates an oscillation signal OSC which oscillates at predetermined frequencies in response to the pumping detection signal PUMP_DET. The pumping unit 30 increases the level of the pumping voltage VPUMP by performing a charge pumping operation when the oscillation signal OSC oscillates.
The pumping voltage detection unit 10 activates the pumping detection signal PUMP_DET when the level of the pumping voltage VPUMP is lower than the reference pumping level PUMP_VREF. On the other hand, the pumping voltage detection unit 10 deactivates the pumping detection signal PUMP_DET when the level of the pumping voltage VPUMP is the same or greater than the reference pumping level PUMP_VREF.
The oscillation signal generation unit 20 generates the oscillation signal OSC, which oscillates at a predetermined first frequency, in response to the activation of the pumping detection signal PUMP_DET. On the other hand, the oscillation signal generation unit 20 generates the oscillation signal OSC, which oscillates at a predetermined second frequency, which is lower than the first frequency, in response to the deactivation of the pumping detection signal PUMP_DET.
The charge pumping operation of the pumping unit 30 is controlled by the oscillation signal OSC. That is, when the oscillation signal OSC oscillates at the first frequency, which is a relatively high frequency, the pumping unit 30 performs a charge pumping operation to generate the pumping voltage VPUMP based on the oscillation signal OSC. On the other hand, when the oscillation signal OSC oscillates at the second frequency, which is a relatively low frequency, the pumping unit 30 infrequently performs or does not perform a charge pumping operation to generate the pumping voltage VPUMP based on the oscillation signal OSC.
FIGS. 2A to 2C illustrates timing diagrams for explaining an operation of the internal voltage generation circuit shown in FIG. 1.
Referring to FIG. 2A, it may be seen that the internal voltage generation circuit of the conventional semiconductor device generates the pumping voltage VPUMP whose level differs depending on a level of the power supply voltage VDD.
Specifically, during a period A where the power supply voltage VDD starts to be supplied to the semiconductor device so that the power supply voltage VDD steadily increases, the level of the power supply voltage VDD may not be sufficiently increased. Therefore, the level of the pumping voltage VPUMP may not be sufficiently increased, either. That is, although not illustrated in the drawing, the level of the pumping voltage VPUMP is lower than the reference pumping level PUMP_VREF. Accordingly, the oscillation signal OSC oscillates at the first frequency, and the level of the pumping voltage VPUMP increases at a relatively high speed through relatively frequent charge pumping operations.
Then, during a period B where the level of the power supply voltage VDD stays the same after a sufficient time elapsed from when the power supply voltage VDD is supplied to the semiconductor device, the operation of the internal voltage generation circuit may significantly differ depending on the level the power supply voltage VDD.
For example, it is assumed that the internal voltage generation circuit generates the pumping voltage VPUMP by pumping the power supply voltage VDD to a three times greater value, and the reference pumping level PUMP_VREF is 3.0V. Referring to FIG. 2B, when the level of the power supply voltage VDD is greater than 1V, that is, the level of the power supply voltage VDD corresponds to 1.0V or 1.1V in FIG. 2A, the level of the pumping voltage VPUMP easily exceeds the reference pumping level PUMP_VREF by the charge pumping operation. Therefore, the oscillation signal OSC oscillates at the second frequency, and the charge pumping operation is performed relatively infrequently. That is, the internal voltage generation circuit operates in a state in which the current consumption caused by the charge pumping operation is minimized.
On the other hand, referring FIG. 2C, when the level of the power supply voltage VDD is lower than 1V, that is, the level of the power supply voltage VDD corresponds to 0.8V or 0.9V in FIG. 2A, the level of the pumping voltage VPUMP is inevitably lower than the reference pumping level PUMP_VREF even though the power supply voltage VDD is continuously pumped. Therefore, the oscillation signal OSC continuously oscillates at the first frequency, and thus, the charge pumping operation is performed relative to the predetermined frequency.
As such, the charge pumping operation may be frequently performed when the level of the power supply voltage VDD is not sufficiently high, even though the level of the pumping voltage VPUMP does not sufficiently increase. In this case, the current may be consumed unnecessarily.